Ec2354 - Vlsi Design 1p1l2h

Question Paper Code : 21373 B.E./B.Tech DEGREE EXAMINATION, MAY/JUNE 2013 Sixth Semester Electronics and Communication Engineering EC 2354/EC 64 – VLSI DESIGN (Regulation 2008) (Common to PTEC 2354 – VLSI Design for B.E. (Part-Time) fifth Semester – Electronics and Communication Engineering – Regulation 2009) Time : Three hours

Maximum : 100 marks Answer ALL questions. PART A – (10 X 2 = 20 marks)

1.

List the various issues in Technology-CAD.

2.

Define the lambda layout rules.

3.

What is meant by design margin?

4.

How do you define the term “device modeling”?

5.

List the various power losses in CMOS circuits.

6.

Enumerate the features of synchronizers.

7.

List the basic types of CMOS testing.

8.

What is meant by logic verification?

9.

Give the Comparison between structural and switch level modelling.

10.

What are gate primitives? Part-B (10 x 2 = 20)

11.

a)

Explain in detail about the ideal I-V characteristics and non ideal I-V characteristics of

(16)

a NMOS and PMOS devices. OR b)

12.

a)

i) Explain in detail about the body effect and its effect in NMOS and PMOS devices.

(8)

ii) Derive the expression for DC transfer characteristics of CMOS Inverter.

(8)

i) Explain in detail about the scaling concept and reliability concept.

(8)

ii) Describe in detail about the transistor sizing for the performance in combinational

(8)

networks.

OR b)

Discuss in detail about the resistive and capacitive delay estimation of a CMOS

(16)

inverter circuit. 13.

a)

Explain in detail about the pipelining concept used in sequential circuits.

(16)

OR b)

Discuss the techniques to reduce switching activity in a static & dynamic CMOS

(16)

circuits. 14.

a)

Explain the design for testability (DFT) concepts

(16)

OR b)

15.

a)

Explain the following i)

Silicon debug principles

(8)

ii)

Boundary scan techniques

(8)

Design and develop the HDL project to realize the function of a priority encoder using

(16)

structural model b)

i) Write a data-flow model verilog HDL program for the two input comparator

(8)

ii) circuit.

(8)

Write a behavioral level verilog HDL program for the 1x8 Multiplexer circuit.